In certain electrical circuit applications, such as those circuits utilized in wireless sensors for Internet of Things (IOT) applications, long battery life for such applications, while maintaining a small sized component, is often required. Such requirements may necessitate that the circuitry is designed to have very low power dissipation. Sensor readout circuitry, ideally, is completely off when such circuitry is not polling sensors, while such circuitry must wake up in the event of desired sensor data acquisition.
In order for such sensor readout circuitry to know when to wake up from its turned-off state, a low frequency oscillator circuit may be utilized to trigger a sensor readout event. Such oscillators may be the only component of the electrical circuit, or the readout component thereof, which is active at all times and, therefore, such circuits are desired to be designed to have minimal power dissipation.
Prior art oscillators have been designed in the past for implementation at low frequency and low power. For example, a low power, low frequency oscillator is exemplified by the circuit 10 of FIG. 1. The circuit 10 includes one or more current sources 11, exemplified by the IRN source and the IRP sources, as shown, a switch module 12 having switches S1 and S2, a capacitor 14 having a capacitance C, a Schmitt trigger 16 designated as P0, and an array 18 of inverters each designated P1, P2, and P3. A reference current either to or from the current source(s) 11 is constantly either charging or discharging the capacitor 14, in response to current flow changes designated by the switching module 12. For example, consider the voltage at the node TOP (VTOP) is below a lower threshold voltage of the Schmitt trigger 16, designated as VST,LOW. In such examples, the output signal of the Schmitt trigger 16, CK0, goes high and the edge from CK0 propagates through the array 18, from P1 to P2 and to P3, to output the CK, clocking signal. In such examples, CK is low and the switching module 12 turns off S2 and turns on S1, which causes the current source 11 to charge C of the capacitor 14 upwards. Alternatively, if VTOP rises above an upper voltage threshold for the Schmitt trigger, VST,HIGH, output of the Schmitt trigger 16, CK0, will go low and, thusly, when inverted by the array 18 with the signal edges propagated throughout, CK will output high to the switching module 12. In such examples, S1 turns off and S2 turns on, which causes the capacitor 14 to discharge C downwards. This oscillation of the clocking signals and charging/discharging of the capacitor 14 repeats so long as current is supplied to the circuit 10. Graphical depiction of the changes and relationships between VTOP, CK0, CK1, and CK is illustrated, graphically, in the depiction of signal voltage versus time in FIG. 2.
When utilizing relaxation oscillators, such as the prior art circuit 10, if the clock frequency is in the range of 1 to 100 Hertz (Hz), then the clock period is in the range of 10 milliseconds (ms) to 1000 ms. Further, the voltage on the TOP node has a rise-to-fall time of up to 500 ms. Due to such slow rise-to-fall timing, the Schmitt trigger 16 may be close to its threshold voltages, either high or low, for long periods of time. In such periods of time, the Schmitt trigger 16 may draw a short current from the current supply 11 to ground, which results in excess power dissipation from the circuit 10. Due to similarly slow clock edges produced by each of the array 18 of inverters, the power dissipation from such inverters may be similarly restrictive. Accordingly, alternative relaxation oscillator circuits, which minimize power dissipation, while operating at low frequency, are desired.
The present disclosure is directed at addressing one or more of the deficiencies and disadvantages set forth above. However, it should be appreciated that the solution of any particular problem is not a limitation on the scope of this disclosure or of the attached claims except to the extent expressly noted.